1. Cross-Reference to Related Application
The subject matter of the present case is related to copending patent application Ser. No. 07/784,493, filed Oct. 29, 1991, now U.S. Pat. No. 5,261,047 entitled Bus Arbitration Scheme For Facilitating Opeation of a Printing Apparatus, to patent application Ser. No. 07/784,481, filed Oct. 29, 1991, now U.S. Pat. No. 5,303,341, entitled Video Processor for a Printing Apparatus, and to patent application Ser. No. 07/784,195, now U.S. Pat. No. 5,276,799 entitled Expandable Electronic Subsystem for a Printing Machine. The pertinent portions of each are incorporated herein by reference.
2. Field of the Invention
The present invention relates generally to an a printing machine, and more particularly to a coprocessing apparatus adapted for use in the printing machine.
3. Description of the Prior Art
It is now well accepted that electronic reprographic systems, such as Canon's NP-9030 digital copying apparatus, have certain distinct advantages over known light-lens systems. The NP-9030 was one of the first electronic reprographic systems to be marketed with the capability to convert an optical image from a scanned original to image intensity signals, and reconstruct the signals, by way of a print engine using a pulsed diode laser. Because of the many image processing capabilities of the electronic reprographic system, which allows for, among other things, cut and paste operations, these types of systems are gaining immensely in popularity. While the NP-9030 was, when first introduced, a revolutionary product, it can no longer keep pace with advancements in the art, many of which are spurred on by advancements in related art areas, such as facsimile and computer.
Advancements in the area of digital design has had a profound effect on the design of electronic reprographic systems. Indeed, in 1990, Xerox launched an electronic reprographic system, known as Docutech, that should serve as a benchmark in the area of electronic reprographics for many years to come. In systems such as Docutech, documents being scanned by an automatic document scanner, also known as an image input terminal (IIT), are processed by an electronic sub-system (ESS) controller and stored in permanent memory pending printing, editing or later use. The ESS of the Docutech system represents a great advancement in the art; however, the highly advanced ESS of Docutech carries a relatively high price, in terms of design and manufacturing. Consequently, to those users who seek some of the advantages of electronic reprograpics, without the potentially inaccessible price tag of Docutech, there continues to be a demand for a system having a relatively high speed, yet inexpensive ESS.
A relatively inexpensive electronic reprographic machine is disclosed in RESEARCH DISCLOSURE, No. 32388, March, 1991. This machine comprises a scanner communicating with a memory section and a Video Processor (VP) by way of a CPU. In one form of operation image data can be transmitted to addresses configured in the memory by the CPU. Moreover, the image data can be retrieved from memory and processed with the VP.
The following patents, which relate to image data transfer in image processing devices, may be of pertinence to the present disclosure:
U.S. Pat. No. 4,580,171 PA1 Patentee: Arimoto PA1 Issued: Apr. 1, 1986 PA1 U.S. Pat. No. 4,800,431 PA1 Patentee: Deering PA1 Issued: Jan. 24, 1989 PA1 U.S. Pat. No. 4,920,427 PA1 Patentee: Hirata PA1 Issued: Apr. 24, 1990 PA1 U.S. Pat. No. 4,931,984 PA1 Patentee: Ny PA1 Issued: Jun. 5, 1990 PA1 U.S. Pat. No. 4,987,529 PA1 Patentee: Craft et al. PA1 Issued: Jan. 22, 1991 PA1 U.S. Pat. No. 5,016,114 PA1 Patentee: Sakata et al. PA1 Issued: May 14, 1991 PA1 U.S. Pat. No. 5,021,892 PA1 Patentee: Kita et al. PA1 Issued: Jun. 4, 1991 PA1 U.S. Pat. No. 5,027,221 PA1 Patentee: Hisatake et al. PA1 Issued: Jun. 25, 1991 PA1 U.S. Pat. No. 5,038,218 PA1 Patentee: Matsumoto PA1 Issued: Aug. 6, 1991 PA1 U.S. Pat. No. 4,169,275 PA1 Patentee: Gunning PA1 Issued: Sep. 25, 1979 PA1 U.S. Pat. No. 4,205,350 PA1 Patentee: Gunning PA1 Issued: May 27, 1980 PA1 U.S. Pat. No. 4,672,186 PA1 Patentee: Van Tyne PA1 Issued: Jun. 9, 1987 PA1 U.S. Pat. No. 4,833,596 PA1 Patentee: Buckland et al. PA1 May 23, 1989 PA1 U.S. Pat. No. 4,920,481 PA1 Patentee: Binkley et al. PA1 Issued: Apr. 24, 1990
U.S. Pat. No. 4,580,171 discloses an image a system in which a reader is coupled with a CPU and an image memory. The memory includes an address counter for sequentially designating addresses to which respective bytes of image data generated by the reader are transferred. As each address is designated by the counter, a memory control signal is transmitted from the CPU to the memory so that the byte can be transferred to or from the memory. An arrangement of a byte counter and a comparator is employed to determine when a preselected number of bytes has been transferred to or from the memory. The preselected number of bytes written into the memory are transferred to a pair of line buffers for subsequent output.
U.S. Pat. No. 4,800,431 discloses a video signal processing device frame buffer controller for storing a frame of an image in its original, intermediate or final form in a frame memory. The frame buffer controller comprises a video input interface, a video output interface, a microprocessor interface and a memory interface. Input data is in an eight bit format, and two successive eight bit chunks are stored in an input buffer so that a sixteen bit format can be transferred to memory through a memory controller. Similarly, in the output interface sixteen bits from the memory are held in a buffer and transmitted to the output eight at a time. This allows the input and output channels to alternate internally while appearing externally to be operating simultaneously. Apparently, data from a system controller, namely a microprocessor, is transferred to the memory controller by way of the input buffer. Hence, it follows that the system controller cannot access the memory controller while image data is being inputted to the input buffer.
U.S. Pat. No. 4,920,427 discloses a facsimile apparatus having multiple bus lines. A first pair of bus lines for carrying image data are coupled with a DMA, a RAM, a disk controller, a data compressor, a data decompressor and a CPU. The CPU is also connected to a third bus, the third bus being connected to a plurality of devices including a working memory (a RAM) for the CPU and a ROM for storing programs used in the CPU. An object of the invention is achieved by inhibiting at least a calling operation during an interval in which a call signal is interrupted so as to prevent "collision" of a receiving operation and the calling operation.
U.S. Pat. No. 4,931,984 discloses a file data retrieving system architecture including: a main bus having a CPU, a memory and a plurality of interfaces connected thereto; an image bus; a pair of data processing units for performing data compression and reproduction, each data processing unit being connected to both the main bus and the image bus; and two display memories, each display memory having data storage capacity corresponding to at least one page of a document of a maximum size, and each display memory being connected to both the main bus and the image bus. The above-described architecture makes it possible to reduce load on the main bus due to a toggle processing of data wherein image data is only transmitted on the image data bus.
U.S. Pat. No. 4,987,529 discloses a bus arbitration control system for a computer system having a microprocessor, a system memory, a memory refresh circuit, a DMA controller, and a plurality of peripheral device bus masters and a shared bus. The arbitration control system gives highest priority to a bus access request signal from the memory refresh circuit. The DMA controller is given second priority access to a shared bus, and the peripheral device bus masters are given next highest priority. The priority rankings of the peripheral device bus masters rotate each time a bus master is granted access to the bus. The microprocessor is given lowest bus access priority except when an interrupt signal must be serviced.
U.S. Pat. No. 5,016,114 discloses a digital copier apparatus with external laser card storage and image compression. In one embodiment of the invention a processor bus is coupled with a main bus and a local bus. An IIT/IOT module, an MPU, a main storage section and an I/O control block are coupled with the processor bus. Additionally, a bit map memory, a compander, a DMAC, a buffer memory and a laser card module are coupled with the main bus. Finally the bit map memory, the compander and the DMAC are also coupled with the local bus. In one example, the buffer memory can be omitted and the compander can be integrated with a FIFO buffer. When the compander and the FIFO are integrated, the buffer memory can be omitted and image data can be fed continuously to the laser card module.
U.S. Pat. No. 5,021,892 discloses an image processing device for controlling data transfer comprising an image scanner, an image printer, a facsimile control unit, a multi-purpose bus, a bidirectional parallel interface unit, and a main CPU. Data can be moved among various input/output units of the device by way of the main CPU. Moreover, the device includes a memory, the memory including a table of I/O codes. The I/O codes can be used to express predetermined combinations of the input/output devices between which data can be transferred.
U.S. Pat. No. 5,027,221 discloses a digital image recording system comprising an IIT, an IOT, a compressor/decompressor arrangement, a controller and a storage unit. The IIT and IOT are coupled with the controller by way of a first bus so that scanning and printing rates of the recording system can be controlled by the controller, while the compressor and decompressor are coupled with the controller by way of a second bus so that compression/decompression rates can be controlled by the controller. The storage unit communicates with the IIT and compressor for permitting temporary or long-term storage of image data generated at the IIT.
U.S. Pat. No. 5,038,218 discloses a digital copying apparatus comprising a video processor coupled with a plurality of input devices and a plurality of output devices. Each input device is selectively coupled with the video processor by way of an input selector while each output device is selectively coupled with the video processor by way of an output selector. The video processor comprises a main control circuit, the main control circuit communicating with the input and output selectors as well as a DMAC, a memory section, a plurality of image manipulation devices and a plurality of input/output devices.
The following patents relate generally to electronic reprographic systems, and may be of pertinence to the present discussion:
U.S. Pat. Nos. 4,169,275 and 4,205,350 each disclose a reproduction scanning system having intermediate storage between input and output scanning stations wherein an input document is scanned in first and second directions, the first direction being orthogonal to the second direction, and the electrical signals being representative of information on the scanned document stored on an intermediate storage member. The information stored in the intermediate storage member may be read out and reproduced on a reproducing medium.
U.S. Pat. No. 4,672,186 discloses a document scanning system which scans printed documents for subsequent storage, retrieval and manipulation. A computer interlaces with a computer I/O bus and printer interface. The computer also controls the operation of a video terminal subsystem through a buffer interface and a synchronous data link control master. A high speed transport system is employed to transport individual documents through image capture stations, machine readers, encoders and sorters.
With the advent of electronic reprographic systems, the demand for multifunctionality will continue to increase. For example, U.S. Pat. No. 5,038,218, which is also discussed above, discloses a personal computer, facsimile apparatus and image read device coupled selectively to a single bus of a video processor by way of an input selector. U.S. Pat. No. 4,897,735 (Patentee: Oneda; Issued: Jan. 30, 1990) also discloses an electronic reprographic machine in which multiple input/output devices, such as a floppy disk device, a scanner and a printer are coupled with a single bus. In an arrangement such as that described in these two patents, data movement can be improved by, among other approaches, data interleaving or increasing bus size. Use of either approach can be undesirable. That is, when using interleaving, data loss can occur if the amount of data becomes too great for the bus to manage. While more data can be managed by using a bus with relatively great width such buses can be expensive as well as noisy. U.S. Pat. No. 5,016,114, which is discussed above, discloses an arrangement in which a plurality of input/output devices are coupled with a plurality of buses. This arrangement, however, functions similarly to a single bus system since the buses, with their respective components, do not appear to operate independently of one another.
To achieve greater cost effectiveness, it has been proposed to use an architecture employing a main processor and a coprocessor. The following patents relate generally to the computer art, and more specifically to coprocessors adapted for respective use with main processors.
U.S. Pat. No. 4,833,596 discloses a system and method for controlling the display of data in a data processing system. The system includes a main processor, a memory subsystem and an input/output subsystem. The input/output subsystem includes an I/O Channel Controller for managing traffic on an I/O bus having an attached coprocessor and a plurality of I/O devices including display devices with different reserved I/O address space. The system and method permit data that is being processed by the system's main processor and data being processed by the system's coprocessor to be displayed individually or in a shared manner selectively on the display devices.
U.S. Pat. No. 4,920,481 discloses a system having an architecture similar to that of the Xerox 6085. The system includes a main processor, a display/memory subsystem and an input/output processor (IOP) subsystem. The IOP subsystem includes a bus to which a plurality of input/output devices are coupled by way of respective controllers. One of the controllers is a rigid disk controller, which rigid disk controller is coupled to the bus via a DMA controller for facilitating data movement. The controllers are serviced by an IOP, the IOP having access to local memory sections. Additionally, a PC emulator is coupled to the bus and an arbiter is coupled with the IOP. Preferably, the arbiter is adapted to arbitrate requests from, among other sources, the DMA controller, the IOP and the PC emulator.
The system disclosed by U.S. Pat. No. 5,016,114 appears to lack flexibility since it only uses one processor to perform a wide variety of tasks. For example, the processor of the '114 patent must take time out to program the DMAC for each data transfer between the bit map memory and the buffer memory. During this time the MPU cannot process image data, so apparently video processing must be temporarily halted.
While the system of U.S. Pat. No. 4,920,481 affords a high level of flexibility, and is well suited for its intended purpose, it is not designed to store substantial quantities of data in the IOP subsystem while concurrently processing data in the main processor. In particular the local memory sections of the IOP subsystem are dedicated to the IOP and are not capable of storing any significant quantities of image. Accordingly when the main processor is busy, any I/O device seeking access to the memory subsystem must hold in a wait state. Such waiting can be inconvenient to a user seeking access to the IOP bus. Moreover, for a given input/output device on the IOP bus, the corresponding data transfer is limited in speed to the data transfer rate of the given input/output device.
It would desirable to provide a system in which the user could input data to a coprocessor substantially concurrent with data being processed in a video processor. Moreover it would desirable to provide the coprocessor with the capability to transfer the data to and receive the data from the video processor in an efficient and timely manner.